Integrated semiconductor memories, such as DRAM (Dynamic Random Access Memory) semiconductor memories, for example, are arranged on a circuit board, for example a motherboard of a computer, and are driven by a memory controller for the purpose of storing or reading out information items. In this case, the output terminals of the memory controller are generally connected to the address and data terminals of the integrated semiconductor product according to a specified standard, for example the JEDEC (Joint Electronic Device Engineering Council) standard. However, the situation arises where it is necessary to deviate from such specified standards for layout reasons.
FIG. 1 shows a memory module including three integrated semiconductor memories 100, 200 and 300, the data terminals 1′, 2′, 3′ and 4′ of which are driven in each case by a memory controller 400. In this case, the memory controller 400 completely shields the memory products 100, 200 and 300 from the module-side driving. Consequently, for an access to memory cells of the memory products, the latter cannot be driven directly externally, but rather only via the memory controller 400 connected upstream. For this purpose, the latter is driven in a manner dependent on a read or write access at a control terminal S, at an address terminal A and in the case of a write access at a data terminal D by data. The memory controller 400 then drives the memory products connected to it via feed lines by means of a standard access protocol.
For the sake of simplicity, in FIG. 1 only data terminals of the data controller are connected to data terminals of the semiconductor products via the feed lines. The driving of control and address terminals of memory products by the memory controller is not illustrated. For driving the three memory products, the memory controller 400 has a total of twelve data terminals arranged in three identical groups. Each of the three groups of data terminals includes the data terminals 1, 2, 3 and 4. According to the standard specified in the example of FIG. 1, the data terminals of the memory controller 400 are intended to be linearly connected in each case to the data terminals of the individual integrated semiconductor memories. This means that the data terminals 1 of the memory controller 400 are intended to be connected to a respective one of the data terminals 1′ of the semiconductor products. Correspondingly, a respective one of the data terminals 2 of the memory controller is intended to be connected to a respective one of the data terminals 2′ of the semiconductor memories, a respective one of the data terminals 3 of the memory controller is intended to be connected to a respective one of the data terminals 3′ of the memory products and a respective one of the data terminals 4 of the memory controller is intended to be connected to a respective one of the data terminals 4′ of the semiconductor memories. For reasons of an efficient layout, however, the data terminals of the semiconductor memory 300 are driven in interchanged fashion by the memory controller 400 in the example of FIG. 1. By way of example, one of the data terminals 1 of the memory controller 400, instead of being connected to the data terminal 1′ of the memory product 300, is connected to the data terminal 2′ thereof. Correspondingly, one of the data terminals 2 of the memory controller 400, instead of being connected to the data terminal 2′ of the memory product 300, is connected to the data terminal 1′ of the semiconductor memory 300. Likewise, in comparison with the wiring of the memory products 100 and 200 with the memory controller 400, the data terminals 3′ and 4′ of the memory product 300 are also driven in interchanged fashion by the memory controller 400.
FIG. 2 shows an enlarged illustration of one of the three groups of data terminals 1, 2, 3 and 4 of the memory controller 400, which are connected to the data terminals 1′, 2′, 3′ and 4′ of the memory product 300 via lines L on a circuit board. The actual memory chip 30 is situated within the housing of the memory product 300. The contacts of the memory chip 30 to the outside world, the so-called pads PD, are connected via bonding wires B to the data terminals, the so-called pins of the memory product 300. Each pad of the memory chip 30 is connected to a register 1″, 2″, 3″ and 4″ of a register circuit R on the memory chip. If data signals are transmitted from the memory controller to the memory cell array via the pads, then said signals are buffer-stored in the register circuit R and from there stored in the memory cells SZ of a memory cell array SZF arranged on the semiconductor memory. The memory cells SZ of the memory cell array are generally arranged along word lines WL and bit lines BL. In the case of DRAM memory cells, a memory cell comprises a storage capacitor SC, which can be connected to a connected bit line BL via a selection transistor AT.
The meaning of the individual pins 1′, 2′, 3′ and 4′ is given by the product pad definition. In the case of standard-conforming wiring, the information present at the pin 1′ is stored via the pad connected to the bonding wire in the register 1″ of the memory product. Likewise, the information items present at the pins 2′, 3′ and 4′ are stored within the product via the corresponding pads in the registers 2″, 3″ and 4″.
In addition to a standard-deviating interchange of data lines between the memory controller and a connected memory product, however, interchanges may also occur among the address lines between the memory controller and the memory products.
If the memory product has been tested as free of defects, however, and the interchange or deviation from a standard with regard to the wiring of data and/or address lines, so-called scrambling, between the memory controller and the memory product is known, the scrambling of the data and/or address terminals does not significantly influence the functioning of the products. In this case, on one memory chip, by way of example, a programmable logic circuit is arranged between the pads and further circuit components of the memory chip which are driven by signals applied to the pads.
U.S. Pat. No. 6,665,782 describes a circuit group including a transmitting unit, for example a camera, and a receiving unit, for example a memory unit for storing digital photographs from the camera. In order to prevent unauthorized users from exchanging data between the transmitting and receiving units, terminals of the camera chip within the transmitting unit are connected via a programmable logic circuit to external output terminals of the transmitting unit. External input terminals of the receiving unit are thus driven with interchanged signals by the transmitting unit. In order to reverse the scrambling within the receiving unit, a further programmable logic circuit is situated between the external input terminals of the receiving unit and terminals of the memory chip of the receiving unit. If the scrambling scheme used in the transmitting unit is known, the programmable logic circuit of the receiving unit can be programmed complementarily with respect to the programmable logic circuit of the transmitting unit in order to resolve the scrambling.
On the other hand, scrambling of data and/or address lines on a memory module becomes problematic and time-consuming, however, when testing the individual memory products on the module. After soldering on the memory products and wiring with the memory controller, the products generally have to be tested anew, since it is not possible to rule out degradation of memory cells within the memory products by the stress in the course of being soldered onto the module circuit board. In order to discover specific defect mechanisms, characteristic data or voltage topologies are written to the memory cell arrays.
If the data topologies are generated within a tester, the actual test program is adapted to the respective module circuit board depending on scrambling of the data and/or address terminals on the module. Depending on the module type, it is thus possible to predefine an adapted line scrambling which is drawn up and maintained for the test run. Furthermore, modern test systems have a logical data scrambler which, in address-dependent fashion, chooses the polarity of the information to be written.
Since the test programs have to be repeatedly rewritten depending on the scrambling used on the circuit board, the method is very time-consuming. If each memory product on a module is wired differently with the memory controller, a dedicated test program has to be used for each memory product and the same test has to be repeated multiply on a module depending on the number of memory products present. The associated outlay for ensuring a high test severity results in increased test costs. If, on the other hand, the individual adaptation of the test programs depending on the line scrambling used on a module test circuit board is dispensed with, individual memory products cannot be tested at all. The consequence is a deficient or not adapted and deterministic test severity.
In addition to the generation of data topologies within a tester, memory modules often also have special circuits, so-called module self-test engines, which can generate corresponding data topologies for testing. On account of the simple and space-saving construction of these circuits, however, the test engines are usually unable to resolve the scrambling. In this case, products whose data and/or address line wiring between the corresponding terminals of the memory controller and of the semiconductor product deviates from the predefined standard cannot be tested at all or can only be tested inadequately.
The document DE 101 31 277 A1 describes a semiconductor memory device having an address decoder device. In an address-decoded operating mode, an applied physical address specifying a physical position of a memory cell in a memory cell array is decoded into an electrical address of the memory cell to be addressed. If physical and electrical address diverge in the case of the semiconductor memory device, then an external test system can directly input the physical address of the memory cell to be addressed into an address input device of the semiconductor memory device. The “address scrambling” is thus effected directly by the address decoder device on the semiconductor memory device. In addition to the address decoder device, a data decoder device may also be provided on the semiconductor memory device. In a similar manner to the “address scrambling”, in a data-decoded operating mode, said data decoder device performs a “data scrambling” if “normal” memory cells, in which a logic “0” is stored for example by means of a negatively charged state and “inverted” memory cells, in which a logic “0” is stored for example by means of a positively charged state, are present.